1. Field of the Invention
The present invention relates to a structure of multilevel interconnects and a fabricating method thereof, and more particularly, to a method of fabricating a microlens with an etching process and a structure thereof.
2. Description of the Prior Art
CMOS image sensors (CISs) and charge-coupled devices (CCDs) are optical circuit components that represent light signals as digital signals. CISs and CCDs are used in the prior art. These two components are widely applied to many devices, including: scanners, video cameras, and digital still cameras. CCDs use is limited in the market due to price and the volume considerations. As a result, CISs enjoy greater popularity in the market.
The CIS is manufactured utilizing the prior art semiconductor manufacturing process. This process helps to decrease the cost and the component size. It is applied in digital products such as personal computer cameras such as Web cams and digital cameras. Currently, the CIS can be classified into two types: line type and plane type. The line type CIS is applied in scanners, and the plane type CIS is applied in digital cameras.
Please refer to FIG. 1 to FIG. 2. FIG. 1 to FIG. 2 show a multilevel interconnects structure of the CIS manufacturing process according to the prior art. As shown in FIG. 1, the conventional CIS includes a pixel array area 102 and a logical circuit area 104 respectively formed on the semiconductor substrate 110, and the pixel array area 102 includes a plurality of shallow trench isolations (STI) 112 and a plurality of photodiodes 114. The logical circuit area 104 includes a plurality of logical components 115. Each photodiode 114 connects electrically to at least one MOS transistor (not shown) such as a reset transistor, current source follower, and row selector. The STI 112 is an insulator between these two adjacent photodiodes 114 for preventing the photodiode 114 from shorting with other components.
An inter layer dielectric (ILD) layer 116 is formed on the semiconductor substrate 110 to cover the photodiodes 114 and the STIs 112, and then a metallization process is performed on the ILD layer 116 to form a first patterned metal layer 118 and a first shielding metal layer 120. The metallizing process includes etching the ILD layer 116, depositing a metal layer such as a copper metal layer on the ILD layer 116, and performing a planarization process such as a chemical mechanical polishing (CMP) process on the metal layer and the ILD layer 116 to form a first patterned metal layer 118 and a first shielding metal layer 120. Since a metal pattern with large superficial measure is always used as a shielding structure in the prior art for the first shielding metal layer 120, the first shielding metal layer 120 has a much greater pattern density than that of the first patterned metal layer 118, and after the planarization process, dishing will occur on the surface of the first shielding metal layer 120 due to the greater pattern density. The rugged and rough problems will also happen in a series of the metallizing processes and the planarization processes afterward, and the problems will become more serious when there are more metallizing processes and planarization processes afterward. As shown in FIG. 2, an inter metal dielectric (IMD) layer 122 is formed on the ILD layer 116, the first patterned metal layer 118, and the first shielding metal layer 120. Next, a second patterned metal layer 124 and a second shielding metal layer 126 are formed on the IMD layer 122, and finally a dielectric layer 128 is deposited on the second patterned metal layer 124 and the second shielding metal layer 126. Obviously, there is a serious rugged and rough problem between the pixel array area 102 and the logical circuit area 104.